Notes about the presentation in the Panel: Not Analyzed - Net unable to be screened. Passed - all values within specified tolerance level for each of the defined rules.įailed - At least one value outside specified tolerance level for one or more of the defined rules (entry associated with violated rule is shaded pale red in color). Use the Menu button or right-click in the table to access the Show/Hide Columns sub-menu, from where you can enable/disable the display of data columns as required.Įach net in the design is assigned one of three possible status settings: The voltage that the signal on the net settles to in the high state. Shows whether the net is routed (full or partial) in the design (True) or totally unrouted (False). The maximum undershoot (ringing below the top value) on the rising edge of the signal. The time it takes for the signal on the net to rise from the threshold voltage (VT), to a valid high (VIH). The maximum overshoot (ringing above the top value) on the rising edge of the signal. The time it takes to drive the signal on the net to the threshold voltage, less the time it would take to drive a reference load (connected directly to the output) to the threshold voltage.
This is the average of the impedance of each track segment, weighted by its length. The average impedance for the net (in Ohms). The total net length (sum of all routed track segments in the net). The maximum undershoot (ringing above the base value) on the falling edge of the signal. The time it takes for the signal on the net to fall from the threshold voltage (VT), to a valid low (VIL). The maximum overshoot (ringing below the base value) on the falling edge of the signal. The time it takes for the signal on the net to fall to the threshold voltage, less the time it would take for a reference load (connected directly to the output) to fall to the threshold voltage. The voltage that the signal on the net settles to in the low state. Information as to why a net can't be analyzed. This column is permanently displayed.Ī textual representation of the net's screening analysis status. The net name and a graphical representation of its status. For each net in the design the following column information can be displayed: The screening results are listed in tabular format. The first time a signal integrity analysis is run for a design a default screening analysis will be performed, using default overshoot/undershoot tolerances and any user-defined signal integrity design rules.
The left-hand side of the panel provides the results from screening analysis of the current design. Alternatively, you can access the panel through the View » Workspace Panels » Editor » Signal Integrity sub-menu entry. Once an analysis has been performed, click the Panels button at the bottom-right of Altium Designer, then choose Signal Integrity from the menu to display the panel. Select Tools » Signal Integrity from the schematic or PCB editor menus to perform a signal integrity analysis on the current design. The Signal Integrity panel is only available after a signal integrity analysis has been performed. The ability to add virtual terminations allows you to ascertain what additional circuitry need be added to the design to resolve these problem areas and hence obtain the most efficient signal integrity performance. These nets can then be analyzed in greater detail by running fast reflection and crosstalk analyses. It enables you to screen all nets in a design, against various defined signal integrity rules, in order to quickly identify problematic nets. The Signal Integrity panel is the control center for performing signal integrity analysis on a design. The Signal Integrity panel is used to configure and control the signal integrity analysis process. It has yet to be updated for the look, feel and possible functionality changes found in the latest version of the software. This document has been imported from the old site.
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